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buildroot/share/PlatformIO/variants/MARLIN_LERDGE/variant.cpp
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297
buildroot/share/PlatformIO/variants/MARLIN_LERDGE/variant.cpp
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/*
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*******************************************************************************
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* Copyright (c) 2017, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*/
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#include "pins_arduino.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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const PinName digitalPin[] = {
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PB_12,
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PB_13,
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PB_14,
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PB_15,
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PD_8,
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PD_9,
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PD_10,
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PD_11,
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PD_12,
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PD_13,
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PD_14,
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PD_15,
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PG_2,
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PG_3,
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PG_4,
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PG_5,
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PG_6,
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PG_7,
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PG_8,
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PC_6,
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PC_7,
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PC_8,
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PC_9,
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PA_8,
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PA_9,
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PA_10,
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PA_11,
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PA_12,
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PA_13,
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PA_14,
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PA_15,
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PC_10,
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PC_11,
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PC_12,
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PD_0,
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PD_1,
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PD_2,
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PD_3,
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PD_4,
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PD_5,
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PD_6,
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PD_7,
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PG_9,
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PG_10,
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PG_11,
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PG_12,
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PG_13,
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PG_14,
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PG_15,
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PB_3,
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PB_4,
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PB_5,
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PB_6,
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PB_7,
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PB_8,
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PB_9,
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PB_10,
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PB_11,
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PE_14,
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PE_15,
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PE_12,
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PE_13,
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PE_10,
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PE_11,
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PE_8,
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PE_9,
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PG_1,
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PE_7,
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PF_15,
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PG_0,
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PF_13,
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PF_14,
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PF_11,
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PF_12,
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PB_2,
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PB_1,
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PC_5,
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PB_0,
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PA_7,
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PC_4,
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PA_5,
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PA_6,
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PA_3,
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PA_4,
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PA_1,
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PA_2,
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PC_3,
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PA_0,
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PC_1,
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PC_2,
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PC_0,
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PF_8,
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PF_6,
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PF_7,
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PF_9,
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PF_10,
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PF_4,
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PF_5,
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PF_2,
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PF_3,
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PF_0,
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PF_1,
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PE_6,
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PC_13,
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PE_4,
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PE_5,
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PE_2,
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PE_3,
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PE_0,
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PE_1,
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PC_14,
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PC_15,
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};
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#ifdef __cplusplus
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}
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#endif
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define __fatal_error(X)
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/**
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* @brief System Clock Configuration
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*
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* The system Clock is configured for F4/F7 as follows:
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 168000000
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* HCLK(Hz) = 168000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = HSE_VALUE
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* PLL_M = HSE_VALUE/1000000
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* PLL_N = 336
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* PLL_P = 2
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* PLL_Q = 7
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 5
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*
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* The system Clock is configured for L4 as follows:
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* System Clock source = PLL (MSI)
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* SYSCLK(Hz) = 80000000
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* HCLK(Hz) = 80000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 1
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* APB2 Prescaler = 1
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* MSI Frequency(Hz) = MSI_VALUE (4000000)
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* LSE Frequency(Hz) = 32768
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* PLL_M = 1
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* PLL_N = 40
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* PLL_P = 7
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* PLL_Q = 2
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* PLL_R = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
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* Flash Latency(WS) = 4
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* @param None
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* @retval None
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*
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* PLL is configured as follows:
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*
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* VCO_IN
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* F4/F7 = HSE / M
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* L4 = MSI / M
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* VCO_OUT
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* F4/F7 = HSE / M * N
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* L4 = MSI / M * N
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* PLLCLK
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* F4/F7 = HSE / M * N / P
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* L4 = MSI / M * N / R
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* PLL48CK
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* F4/F7 = HSE / M * N / Q
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* L4 = MSI / M * N / Q USB Clock is obtained over PLLSAI1
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*
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* SYSCLK = PLLCLK
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* HCLK = SYSCLK / AHB_PRESC
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* PCLKx = HCLK / APBx_PRESC
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*
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* Constraints on parameters:
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*
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* VCO_IN between 1MHz and 2MHz (2MHz recommended)
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* VCO_OUT between 192MHz and 432MHz
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* HSE = 8MHz
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* M = 2 .. 63 (inclusive)
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* N = 192 ... 432 (inclusive)
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* P = 2, 4, 6, 8
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* Q = 2 .. 15 (inclusive)
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*
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* AHB_PRESC=1,2,4,8,16,64,128,256,512
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* APBx_PRESC=1,2,4,8,16
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*
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* Output clocks:
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*
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* CPU SYSCLK max 168MHz
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* USB,RNG,SDIO PLL48CK must be 48MHz for USB
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* AHB HCLK max 168MHz
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* APB1 PCLK1 max 42MHz
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* APB2 PCLK2 max 84MHz
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*
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* Timers run from APBx if APBx_PRESC=1, else 2x APBx
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*/
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void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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__PWR_CLK_ENABLE();
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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__fatal_error("HAL_RCC_OscConfig");
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}
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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__fatal_error("HAL_RCC_ClockConfig");
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}
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/**Configure the Systick interrupt time */
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
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/**Configure the Systick */
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
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}
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#ifdef __cplusplus
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}
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#endif
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